library verilog;
use verilog.vl_types.all;
entity filter is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        data            : in     vl_logic_vector(7 downto 0);
        fil_output      : out    vl_logic_vector(7 downto 0);
        error           : out    vl_logic_vector(7 downto 0)
    );
end filter;
